Logic Design Engineer

Logic Design Engineer

CaPow is growing! We are looking for an ASIC/FPGA Logic Design Engineer to join our design team and take an integral role in developing our cutting-edge ASIC controller for wireless energy transfer systems.
Our in-house developed controller includes complex processing units packed as an integrated high-performance power manager which resemble the heart of the company’s innovation.

Joining CaPow’s Logic design team will give you the unique opportunity to engage in the entire chip definition and development flow, starting from system and architecture stage and up to production. As a Front-end Design Engineer, you will be responsible for the most critical phase of defining, maintaining and implementing the logical core of CaPow’s top-notch SoC technology along its way into silicon.

We are looking for a Logic Design Engineer with significant understanding of ASIC/FPGA engineering concepts, knowledge in RTL design methodologies and excellent analytical and technical skills to join our team and take part in our revolutionary product.

Key Responsibilities:

  • Define and develop complex digital IPs – starting from the architectural conceptual stage and up to RTL realization.
  • Performing detailed design, coding and verification for ASIC/FPGA
  • Modify existing FPGA designs and manage a clean transition into the ASIC environment.
  • Document Chip/Block level design parameters, such as interface protocols, internal flow diagrams and IO’s.
  • Take ownership of the full RTL integration: top-level specifications, DFT specifications, gate level synthesis, STA work and timing/power closure.
  • Perform functional/gate-level simulations and debug your work as needed.
  • Support in the verification process including DFT tests.
  • Collaborate with SW and HW teams.


  • B.Sc. in Electrical/Computer engineering
  • At least 5 years of experience in RTL design
  • Knowledge in principles regarding the FPGA field (Altera/Xilinx/Microchip)
  • Knowledge in relevant programming and scripting languages (TCL/Python)
  • Good knowledge of C / C++
  • Familiarity with communication protocols and memories
  • Experience with PMIC’s – Huge Advantage
  • Experience with Asynchronous logic design – Advantage
  • Familiarity with physical backend flow – Advantage

Contact: jobs@capow.energy